1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, it relates to what is called a CB/CV continuous contact structure which is located between select gates of a NAND flash memory and in which a lower contact layer (lower contact CB) and an upper contact layer (upper contact CV) are coupled together.
2. Description of the Related Art
Recently, a CB/CV continuous contact structure has been used in a semiconductor integrated circuit device (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-297830). The CB/CV continuous contact structure is located between select gates (SG, SG) in, for example, a NAND flash memory, and in this structure, a lower contact (CB) connected to a substrate (lower interconnect) is directly coupled to an upper contact (CV) connected to an upper M1 interconnect.
In the case of the NAND flash memory using this CB/CV continuous contact structure, the lower contact (CB) is limited in the dimension (length of the long-side direction of a CB pattern) in its width direction perpendicular to the select gate (SG) in order to prevent a dielectric breakdown (short-circuit) due to proximity to the select gate (SG). Moreover, the upper contact (CV) is limited in the dimension (length of the short-side direction of a CV pattern) in its width direction in which this upper contact adjoins the M1 interconnect in order to prevent a dielectric breakdown due to proximity to the M1 interconnect.
Thus, in the CB/CV continuous contact structure, limitations differ between on the lower contact (CB) and the upper contact (CV).